Flash memory devices typically are electrically erasable and/or programmable and are often used for data storage in relatively large units. Flash memory is widely used, for example, for storing a basic input/output system (BIOS) in place of a hard disk, for storing a communication protocol in a mobile phone, as an image memory in a digital camera, and other storage applications.
NOR-type flash memory devices typically have a significantly greater programming and read speed in comparison to other types of nonvolatile memory devices. A typical NOR-type flash memory device includes memory cells positioned at respective intersections of word lines and bit lines. Each memory cell typically includes a control gate and a floating gate positioned between a source region and a drain region. The control gates typically are coupled to word lines, the drain regions are typically coupled in common to a bit line, and the source region is typically grounded. The floating gate typically is disposed between a channel region and the control gate.
FIG. 1 is a block diagram schematically illustrating a conventional NOR-type flash memory device. Memory blocks BLK, 10, 12, 14 and 16 and a sense amplifier (S/A) 20 are illustrated. For example, the memory block 10 may have 512K memory cells, the number of word lines WL may be 1024 and the number of bit lines BL may be 512. The word lines are connected to row decoders X-DEC, 30 and 31, and the bit lines are selectively connected to the sense amplifier 20 through a column pass circuit Y-PASS 40 in response to a column decoded signal output from a column decoder. A row decoder may select one word line and a column decoder may select one bit line. The sense amplifier 20 senses whether a selected cell is an “off” cell or “on” cell, amplifying a bit line voltage according to a state of a memory cell connected to a selected word line and selected bit line.
FIG. 2 is a circuit diagram illustrating a memory cell of a memory block of the memory device of FIG. 1. A memory cell includes a cell transistor CTR1. The cell transistor CTR1 includes a control gate and a floating gate. The control gate is connected to a word line WL. A drain of the cell transistor CTR1 is connected to a bit line BL and a source is connected to a ground terminal through a source line SL.
FIG. 3 is a circuit diagram illustrating a conventional read operation of a NOR-type flash memory device as illustrated in FIGS. 1 and 2. When a cell transistor CTR10 is selected, a word line S_WL and a bit line S_BL connected to the cell transistor CTR10 are selected. Other word lines US_WL connected to other cell transistors CTR12-15 in other rows of cell transistors are unselected, and a bit line US-BL connected to cell transistors CTR11, CTR13, CTR15 is unselected. The selected bit line S_BL is selected by coupling it to the sense amplifier S/A using a column pass transistor SW1 in response to a column selection signal yi. The unselected bit line US-BL is disconnected from the sense amplifier S/A by turning off a column pass transistor SW2 in response to another column selection signal yj.
In a read operation, when a voltage, e.g., 5V, is applied to the selected word line S_WL, and 0V is applied to the unselected word lines US_WL, and the selected cell transistor CTR10 connected to the selected word line S_WL and the selected bit line S_BL is an “off” cell, cell current Icell may be approximately 0, which causes the voltage of the selected word line S_BL, which is precharged, to remain at a logic “high” value. If the selected cell transistor CTR10 is an “on” cell, cell current Icell has a larger value which, after passage of a certain amount of time, causes the voltage of the selected bit line S_BL to approach a logic “low.” To read a state of the selected cell, the sense amplifier S/A is turned on at an appropriate time point in response to the column selection signal yi and performs a sense and amplification operation.
FIG. 4 is a circuit diagram illustrating a conventional program operation of a NOR-type flash memory device. To program a selected cell transistor CTR20 connected to a word line S_WL and a bit line S_BL to an “off” condition, a program voltage, for example, 10V, is applied to the selected word line S_WL. A bias voltage, for example, 5V, is applied to the selected bit line S_BL, while unselected word lines US_WL connected to unselected cell transistors CTR21, CTR22, a source line SL, and unselected bit lines (not shown) are grounded. This bias condition supports a program scheme using a channel hot electron (CHE) injection, in which a threshold voltage of cell transistor is increased by injecting hot electrons into a floating gate of the selected cell CTR20. The programmed flash memory cell CTR20 prevents current flow from a drain region thereof to a source region thereof.
FIG. 5 is a circuit diagram illustrating a conventional erase operation for a NOR-type flash memory device. To erase a memory cell transistor CTR51, a bit line BL and a source line SL are floated. A negative voltage, for example, −8V, is applied to a word line WL. A bulk voltage Vbulk, for example, 8V, is applied to a substrate of the cell transistor CTR51. The word line voltage and substrate (bulk) voltage are examples, and other voltage levels may be used. Electrons in the floating gate move via Fowler-Nordheim (FN) tunneling through a tunnel oxide layer to the semiconductor substrate. The tunneling may be induced by forming a relatively high electric field between the floating gate of the memory cell CTR51 and the semiconductor substrate.
As described above, a high electric field is typically generated between a floating gate of memory cell and a semiconductor substrate, thereby generating the Fowler-Nordheim tunneling (F-N tunneling) toward the semiconductor substrate When electrons in the floating gate excessively tunnel through the semiconductor substrate, the threshold voltage of cell transistor may be taken below 0V, which may be referred to as over erase. Over erase may cause a drain turn-on failure, which can prevent accurate reading of a cell.
FIGS. 6 and 7 are drawings that illustrate such a failure. In particular, FIG. 6 is a circuit diagram showing peripheral cells adjacent to the over erased cells in an erase operation, and FIG. 7 is a graph illustrating the threshold voltage distribution of the over erased cells. Referring to FIGS. 6 and 7, if a cell CTR62 is over erased, the threshold voltage distribution may be illustrated as shown in FIG. 7. In particular, the threshold voltage of the over erased cell CTR62 may fall into the region 70 of the threshold voltage distribution. In this case, when 5V is applied to a word line S_WL of a selected cell transistor CTR61 and word lines US_WL connected to unselected cells CTR62, CTR63 are grounded, the over erased cell CTR62 may be turned on because of its low threshold voltage.
Assuming that the selected cell CTR61 is an “off” cell, the current flowing into the grounded terminal through the source line SL from the selected bit line S_BL would be close to 0 if there were no over erased cells. However, when the unselected cell CTR62 is over erased, current passes through the unselected cell CTR62 and, consequently, the selected cell CTR61 is erroneously read as “on” cell. Such erroneous turn-on may occur in a writing operation as well.
FIG. 8 is a detailed circuit diagram illustrating a decoder for driving the word lines as shown in FIG. 6. A read global word line GWL_RD is used to select a set of local word lines WL<0>-WL<7> in a read operation and a write global word line GWL_WT is used to select local word lines WL<0>-WL<7> in a write (program) operation. In read and write operations, the local word lines WL<0>-WL<7> are driven responsive to partial word lines PWL<0>-PWL<7>.
The decoder selects one local word line by combination of signals that are applied to the global word line and the partial word line. For example, to select the local word line WL<0> in a reading operation, the read global word line GWL_RD is driven to a “high” level, thereby turning on an NMOS transistor NM81. The current driving capability of the PMOS transistors PM81, PM82 is less than that of the NMOS transistor NM81, causing the node N80 to be driven from a voltage Vpx towards the voltage of a line nSS_RD, which is held at around 0V in a read operation. With reference to the node N80, the node N80 maintains voltage of Vpx in a normal operation, and voltage of 0V when selecting the global word line GWL_RD or GWL_WT.
When a partial word line PWL<0> is selected, the corresponding local word line WL<0> is driven to the same voltage as the partial word line PWL<0>, e.g., around 5V. The other partial word lines PWL<1>-PWL<7> are held at around 0V, such that the local word lines WL<1>-WL<7> are driven to around 0V.
If neither the read global word line GWL_RD nor the write global word line GWL_WT is selected, the node N80 has a voltage of Vpx and, consequently, the NMOS transistors NM83, NM85 of the local word line drivers 80-87 are turned on. If the partial word lines PWL<0>-PWL<7> are held at around 0V, complementary partial word lines nPWL<0>-nPWL<7> have a complementary voltage VCC, thereby turning on the NMOS transistors NM84, NM86. As a result, the local word lines WL<0>-WL<7> are driven to an external voltage Vex, which may be, for example, a ground voltage.
However, as described above, if memory cells connected to anyone of local word lines are over erased, a drain turn-on problem may occur because the ground voltage applied to unselected word lines may cause an error as discussed above.